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| FAN6300 -- Highly Integrated Quasi-Resonant Current Mode PWM Controller June 2008 FAN6300 Highly Integrated Quasi-Resonant Current Mode PWM Controller Features High-Voltage Startup Quasi-Resonant Operation Cycle-by-Cycle Current Limiting Peak-Current-Mode Control Leading-Edge Blanking Internal Minimum tOFF Internal 2ms Soft-Start Over-Power Compensation GATE Output Maximum Voltage Auto-Recovery Short-Circuit Protection (FB Pin) Auto-Recovery Open-Loop Protection (FB Pin) VDD Pin & Output Voltage (DET Pin) OVP Latched Description The highly integrated FAN6300 PWM controller provides several features to enhance the performance of flyback converters. A built-in HV startup circuit can provide more startup current to reduce the startup time of the controller. Once the VDD voltage exceeds the turn-on threshold voltage, the HV startup function is disabled immediately to improve power consumption. An internal valley voltage detector ensures the power system operates at Quasi-Resonant operation in widerange line voltage and any load conditions and reduces switching loss to minimize switching voltage on drain of power MOSFET. To minimize standby power consumption and light-load efficiency, a proprietary green-mode function provides off-time modulation to decrease switching frequency and perform extended valley voltage switching to keep to a minimum switching voltage. FAN6300 controller also provides many protection functions. Pulse-by-pulse current limiting ensures the fixed peak current limit level, even when a short circuit occurs. Once an open-circuit failure occurs in the feedback loop, the internal protection circuit disables PWM output immediately. As long as VDD drops below the turn-off threshold voltage, controller also disables PWM output. The gate output is clamped at 18V to protect the power MOS from high gate-source voltage conditions. The minimum tOFF time limit prevents the system frequency from being too high. If the DET pin reaches OVP, internal OTP is triggered, and the power system enters latch-mode until AC power is removed. FAN6300 controller is available in both 8-pin DIP and SOP packages. Applications AC/DC NB Adapters Open-Frame SMPS Ordering Information Part Number FAN6300DZ FAN6300SZ Operating Temperature Range -40 to +105C -40 to +105C Eco Status RoHS RoHS Package 8-Lead, Dual Inline Package (DIP) Packing Method Tube 8-Lead, Small Outline Package (SOP) Reel & Tape For Fairchild's definition of "green" Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. (c) 2007 Fairchild Semiconductor Corporation FAN6300 * Rev. 1.0.1 www.fairchildsemi.com FAN6300 -- Highly Integrated Quasi-Resonant Current Mode PWM Controller Application Diagram Figure 1. Typical Application Internal Block Diagram HV 8 4.2V IHV 27V OVP VDD 6 Internal Bias Two Steps UVLO 16V/10V/8V FB 2 Soft-Start 2ms 2R Latched R 500s 30s Timer 55ms FB OLP Starter CS 3 Blanking Circuit PWM Current Limit IDET Latched tOFF-MIN (8s/38s) 0.3V VDET VDET Latched 2.5V DET OVP Valley Detector 1st Valley DRV S SET Q 18V 5 GATE Over-Power Compensation R CLR Q tOFF-MIN +9s tOFF Blanking (4s) S/H DET 1 5V IDET 0.3V Internal OTP Latched 4 GND 7 NC Figure 2. Functional Block Diagram (c) 2007 Fairchild Semiconductor Corporation FAN6300 * Rev. 1.0.1 www.fairchildsemi.com 2 FAN6300 -- Highly Integrated Quasi-Resonant Current Mode PWM Controller Marking Information F- Fairchild logo Z- Plant Code X- 1 digit year code Y- 1 digit week code TT: 2 digits die run code T: Package type (D=DIP, S=SOP) P: Z: Pb free, Y: Green package M: Manufacture flow code Figure 3. Marking Information (c) 2007 Fairchild Semiconductor Corporation FAN6300 * Rev. 1.0.1 www.fairchildsemi.com 3 FAN6300 -- Highly Integrated Quasi-Resonant Current Mode PWM Controller Pin Configuration Figure 4. Pin Configuration Pin Definitions Pin # Name Description This pin is connected to an auxiliary winding of the transformer via resistors of the divider for the following purposes: - Generates a ZCD signal once the secondary-side switching current falls to zero. - Produces an offset voltage to compensate the threshold voltage of the peak current limit to provide a constant power limit. The offset is generated in accordance with the input voltage when PWM signal is enabled. - Detects the valley voltage of the switching waveform to achieve the valley voltage switching and minimize the switching losses. A voltage comparator and a 2.5V reference voltage develop an output OVP protection. The ratio of the divider decides what output voltage to stop gate, as an optical coupler and secondary shunt regulator are used. The Feedback pin is supposed to be connected to the output of the error amplifier for achieving the voltage control loop. The FB should be connected to the output of the optical coupler if the error-amplifier is equipped at the secondary-side of the power converter. 2 FB For the primary-side control application, this pin is applied to connect a RC network to the ground for feedback-loop compensation. The input impedance of this pin is a 5k equivalent resistance. A 1/3 attenuator connected between the FB and the PWM circuit is used for the loop gain attenuation. FAN6300 performs an open-loop protection once the FB voltage is higher than a threshold voltage (around 4.2V) more than 55ms. 3 4 5 6 7 8 CS GND GATE VDD NC HV Input to the comparator of the over-current protection. A resistor senses the switching current and the resulting voltage is applied to this pin for the cycle-by-cycle current limit. The threshold voltage for peak current limit is 0.8V. The power ground and signal ground. A 0.1F decoupling capacitor placed between VDD and GND is recommended. Totem-pole output generates the PWM signal to drive the external power MOSFET. The clamped gate output voltage is 18V. Power supply. The threshold voltages for startup and turn-off are 16V and 10V. The startup current is less than 20A and the operating current is lower than 4.5mA. No connect. High-voltage startup. 1 DET (c) 2007 Fairchild Semiconductor Corporation FAN6300 * Rev. 1.0.1 www.fairchildsemi.com 4 FAN6300 -- Highly Integrated Quasi-Resonant Current Mode PWM Controller Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VDD VHV VH VL PD TJ TSTG TL ESD HV Pin GATE Pin VFB, VCS, VDET Parameter DC Supply Voltage Min. Max. 30 500 Unit V V V V mW mW C C C KV V -0.3 -0.3 SOP-8 DIP-8 -55 25.0 7.0 400 800 +150 +150 +270 2.0 200 Power Dissipation Operating Junction Temperature Storage Temperature Range Lead Temperature, Soldering 10 Seconds ESD Capability, Human Body Model ESD Capability, Machine Model Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 2. All voltage values, except differential voltages, are given with respect to GND pin. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol TA Parameter Operating Ambient Temperature Min. -40 Max. +105 Unit C (c) 2007 Fairchild Semiconductor Corporation FAN6300 * Rev. 1.0.1 www.fairchildsemi.com 5 FAN6300 -- Highly Integrated Quasi-Resonant Current Mode PWM Controller Electrical Characteristics VDD=15V, TA=25, unless otherwise specified. Symbol VDD SECTION VOP VDD-ON VDD-PWM-OFF VDD-OFF IDD-ST IDD-OP IDD-PWM-OFF VDD-OVP tVDD-OVP Parameter Continuously Operating Voltage Turn-on Threshold Voltage PWM Off Threshold Voltage Turn-Off Threshold Voltage Startup Current Operating Current Operating Current at PWM-Off Phase VDD Over-Voltage Protection (Latch-Off) VDD OVP Debounce Time Conditions Min. Typ. Max. 25 Units V V V V 16 10 8 0V< VDD < VDD-ON GATE Open VDD=15V, fs=60KHz, CL=2nF VDD=VDD-PWM-OFF-0.5V 4.5 80 27 150 VAC=90V (VDC=120V), VDD=0V HV=500V, VDD=VDD-OFF +1V AV=VCS/VFB 0 HV START-UP CURRENT SOURCE SECTION IHV IHV-LC Supply Current Drawn From HV Pin Leakage Current After Startup 1.2 1 20 mA A FEEDBACK INPUT SECTION AV ZFB IOZ VOZ VFB-OLP tD-OLP tSS VDET-OVP VV-HIGH VV-LOW tDET-OVP IDET-SOURCE VDET-HIGH VDET-LOW tOFF-BNK Input-voltage to Current Sense Attenuation Input Impedance Bias Current Zero Duty Cycle Input Voltage Open-Loop Protection Threshold Voltage Debounce Time for Open-Loop / Overload Protection Internal Soft-Start Time Comparator Reference Voltage Output High Voltage Output Low Voltage Output OVP (Latched) Debounce Time Maximum Source Current Upper Clamp Voltage Lower Clamp Voltage Leading-Edge Blanking Time for DET(3) OVP, PWM MOS Turns Off 0.1 0.3 4 100 150 1.6 2.45 4.5 0.5 200 1 5 3.9 1/2.75 3 1/3.00 5 1.2 1 4.2 55 2.0 2.50 2.4 2.55 4.5 1/3.25 7 2.0 V/V K mA V V ms ms V V V s mA V V s DET PIN OVP AND VALLEY DETECTION SECTION Note: 3. Guaranteed by design. (c) 2007 Fairchild Semiconductor Corporation FAN6300 * Rev. 1.0.1 www.fairchildsemi.com 6 FAN6300 -- Highly Integrated Quasi-Resonant Current Mode PWM Controller Electrical Characteristics (Continued) VDD=15V, TA=25, unless otherwise specified. Symbol tON-MAX tOFF-MIN VN VG VFBG tSTARTER tTIME-OUT Parameter Maximum On Time Minimum Off Time (Maximum Frequency) Beginning of Green-On Mode at FB Voltage Level Beginning of Green-Off Mode at FB Voltage Level Green-Off Mode VFB Hysteresis Voltage Start Timer (Time-out Timer) Timeout After tOFF-MIN (If No Valley Signal) Output Voltage Low Output Voltage High Rising Time Falling Time GATE Output Clamping Voltage Delay to Output Cycle-by-cycle Current Limit Threshold Voltage Slope Compensation Leading Edge Blanking Time (MOS Turns On) VCS Camped High Voltage Delay Time Conditions Min. 40 Typ. 45 8 38 2.1 1.2 0.1 Max. 50 Units s s s V V V s s s OSCILLATOR SECTION VFBVN VFB=VG VFB 500 30 9 OUTPUT SECTION VOL VOH tR tF VCLAMP tPD VLIMIT VSLOPE tBNK VCS-H tCS-H VDD=15V, IO=150mA VDD=12V, IO=150mA 7.5 120 60 17 18 150 0.75 tON=45s tON=0s 225 CS Pin Floating CS Pin Floating 4.5 100 150 0.80 0.3 0.1 300 375 5.0 200 19 250 0.85 1.5 V V ns ns V ns V V V ns V s CURRENT SENSE SECTION (c) 2007 Fairchild Semiconductor Corporation FAN6300 * Rev. 1.0.1 www.fairchildsemi.com 7 FAN6300 -- Highly Integrated Quasi-Resonant Current Mode PWM Controller Typical Performance Characteristics These characteristic graphs are normalized at TA = 25C. 17.0 10.5 10.3 V DD-P WM-OFF (V) -40 -25 -10 5 20 35 50 65 80 95 110 125 16.5 V DD-ON (V) 10.1 9.9 9.7 9.5 -40 -25 -10 5 20 35 50 65 80 95 110 125 16.0 15.5 15.0 Temperature Temperature Figure 5. Turn-on Threshold Voltage Figure 6. PWM Off Threshold Voltage 8.2 8.1 10 9 V DD-OFF (V) 7.9 7.8 7.7 7.6 -40 -25 -10 5 20 35 50 65 80 95 110 125 IDD-S T (uA) 8.0 8 7 6 5 4 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature Temperature Figure 7. Turn-off Threshold Voltage Figure 8. Startup Current 5.2 5.0 2.2 2.0 IDD-OP (mA) 4.6 4.4 4.2 4.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 IHV (mA) 4.8 1.8 1.6 1.4 1.2 1.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature Temperature Figure 9. Operating Current Figure 10. Supply Current Drawn From HV Pin 1.0 0.8 0.6 0.4 0.2 0.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 0.30 V DE T-LOW (V) 0.25 IHV-LC (uA) 0.20 0.15 0.10 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature Temperature Figure 11. Leakage Current After Startup Figure 12. Lower Clamp Voltage (c) 2007 Fairchild Semiconductor Corporation FAN6300 * Rev. 1.0.1 www.fairchildsemi.com 8 FAN6300 -- Highly Integrated Quasi-Resonant Current Mode PWM Controller Typical Performance Characteristics These characteristic graphs are normalized at TA = 25C. 2.6 9.0 2.6 8.5 V DE T-OVP (V) 2.5 tOFF-MIN (us) -40 -25 -10 5 20 35 50 65 80 95 110 125 8.0 2.5 7.5 2.4 7.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature Temperature Figure 13. Comparator Reference Voltage Figure 14. Minimum Off Time (VFB>VN) 40 39 600 575 tS TAR TE R (us) tOFF-MIN (us) 550 525 500 475 450 38 37 36 35 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature Temperature Figure 15. Minimum Off Time (VFB=VG) Figure 16. Start Timer (VFB www.fairchildsemi.com 9 FAN6300 -- Highly Integrated Quasi-Resonant Current Mode PWM Controller Operation Description The FAN6300 of PWM controller integrates designs to enhance the performance of flyback converters. An internal valley voltage detector ensures power system operates at Quasi-Resonant (QR) operation in a wide range of line voltage. The following descriptions highlight some of the features of the FAN6300 series. Green-mode Operation The proprietary green-mode function provides off-time modulation to linearly decrease the switching frequency under light-load conditions. VFB, which is derived from the voltage feedback loop, is taken as the reference. In Figure 19, once VFB is lower than VN, the tOFF-MIN time increases linearly with lower VFB. The valley voltage detection signal does not start until the tOFF-MIN time finishes. Therefore, the valley detect circuit is activated until the tOFF-MIN time finishes, which decreases the switching frequency and provides extended valley voltage switching. However, in very light load condition, it might fail to detect the valley voltage after the tOFF-MIN expires. Under this condition, an internal tTIME-OUT signal initiates a new cycle start after a 9s delay. Figure 20 and Figure 21 show the two different conditions. Startup Current For startup, the HV pin is connected to the line input or bulk capacitor through an external diode and resistor, RHV, which are recommended as 1N4007 and 100k. Typical startup current drawn from pin HV is 1.2mA and it charges the hold-up capacitor through the diode and resistor. When the VDD voltage level reaches VDD-ON, the startup current switches off. At this moment, the VDD capacitor only supplies the FAN6300 to maintain VDD until the auxiliary winding of the main transformer provides the operating current. Valley Detection The DET pin is connected to an auxiliary winding of the transformer via resistors of the divider to generate a valley signal once the secondary-side switching current discharges to zero. It detects the valley voltage of the switching waveform to achieve the valley voltage switching. This ensures QR operation, minimizes switching losses, and reduces EMI. Figure 17 shows divider resistors RDET and RA. RDET is recommended as 150k to 220k to achieve valley voltage switching. When VAUX (in Figure 17) is negative, the DET pin voltage is clamped to 0.3V. Figure 19. VFB vs. tOFF-MIN Curve Figure 17. Valley Detect Section The internal timer (minimum tOFF time) prevents gate retriggering within 8s after the gate signal going-low transition. The minimum tOFF time limit prevents the system frequency being too high. Figure 18 shows a typical drain voltage waveform with first valley switching. Figure 20. QR Operation in Extended Valley Voltage Detection Mode Figure 18. First Valley Switching (c) 2007 Fairchild Semiconductor Corporation FAN6300 * Rev. 1.0.1 Figure 21. Internal tTIME-OUT Initiates New Cycle After Failure to Detect Valley Voltage (with 9s Delay) www.fairchildsemi.com 10 FAN6300 -- Highly Integrated Quasi-Resonant Current Mode PWM Controller Current Sensing and PWM Current Limiting Peak-current-mode control is utilized to regulate output voltage and provide pulse-by-pulse current limiting. The switch current is detected by a sense resistor into the CS pin. The PWM duty cycle is determined by this current sense signal and VFB. When the voltage on CS pin reaches around VLIMIT = (VFB-1.2)/3, the switch cycle is terminated immediately. VLIMIT is internally clamped to a variable voltage around 0.8V for output power limit. VDD Over-Voltage Protection VDD over-voltage protection prevents damage due to abnormal conditions. Once the VDD voltage is over the VDD over-voltage protection voltage (VDD-OVP) and lasts for tVDDOVP, the PWM pulse is disabled until the VDD voltage drops below the UVLO, then starts again. Output Over-Voltage Protection The output over-voltage protection works by the sampling voltage, as shown in Figure 23, after switch-off sequence. A 4s blanking time ignores the leakage inductance ringing. A voltage comparator and a 2.5V reference voltage develop an output OVP protection. The ratio of the divider determines the sampling voltage of the stop gate, as an optical coupler and secondary shunt regulator are used. If the DET pin OVP is triggered, power system enters latch-mode until AC power is removed. Leading Edge Blanking (LEB) Each time the power MOFFET switches on, a turn-on spike occurs on the sense resistor. To avoid premature termination of the switching pulse, lead-edge blanking time is built in. During the blanking period, the current limit comparator is disabled; it cannot switch off the gate driver. Under-Voltage Lockout (UVLO) The turn-on, PWM-off, and turn-off thresholds are fixed internally at 16/10/8V. During startup, the startup capacitor must be charged to 16V through the startup resistor to enable the IC. The hold-up capacitor continues to supply VDD until energy can be delivered from the auxiliary winding of the main transformer. VDD must not drop below 10V during this startup process. This UVLO hysteresis window ensures that hold-up capacitor is adequate to supply VDD during startup. Gate Output The BiCMOS output stage is a fast totem-pole gate driver. Cross conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. The output driver is clamped by an internal 18V Zener diode to protect power MOSFET transistors against undesired over-voltage gate signals. Figure 23. Voltage Sampled After 4s Blanking Time After Switch-off Sequence Short-Circuit and Open-Loop Protection The FB voltage increases every time the output of the power supply is shorted or overloaded. If the FB voltage remains higher than a built-in threshold for longer than tD-OLP, PWM output is turned off. As PWM output is turned-off, the supply voltage VDD begins decreasing. When VDD goes below the PWM-off threshold of 10V, VDD decreases to 8V, then the controller is totally shut down. VDD is charged up to the turn-on threshold voltage of 16V through the startup resistor until PWM output is restarted. This protection feature continues as long as the overloading condition persists. This prevents the power supply from overheating due to overloading. Over-Power Compensation To compensate this variation for wide AC input range, the DET pin produces an offset voltage to compensate the threshold voltage of the peak current limit to provide a constant-power limit. The offset is generated in accordance with the input voltage when PWM signal is enabled. This results in a lower current limit at high-line inputs than low-line inputs. At fixed-load condition, the CS limit is higher when the value of RDET is higher. RDET also affects the H/L line constant power limit. Figure 22. H/L Line Constant Power Limit Compensated by DET Pin (c) 2007 Fairchild Semiconductor Corporation FAN6300 * Rev. 1.0.1 www.fairchildsemi.com 11 FAN6300 -- Highly Integrated Quasi-Resonant Current Mode PWM Controller Physical Dimensions C 8 5 1 b 4 e D A1 A Figure 24. 8-Lead, Small Outline Package (SOP) Dimensions Symbol A A1 b c D E e F H L 5.791 0.406 0 4.648 3.810 1.016 1.270 0.381X45 6.197 1.270 8 0.228 0.016 0 Millimeter Min. 1.346 0.101 0.406 0.203 4.978 3.987 1.524 0.183 0.150 0.040 0.050 0.015X45 0.244 0.050 8 Typ. Max. 1.752 0.254 Min. 0.053 0.004 0.016 0.008 0.196 0.157 0.060 Inch Typ. Max. 0.069 0.010 Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. (c) 2007 Fairchild Semiconductor Corporation FAN6300 * Rev. 1.0.1 H F E L www.fairchildsemi.com 12 FAN6300 -- Highly Integrated Quasi-Resonant Current Mode PWM Controller Physical Dimensions (Continued) D 8 5 X E1 E eB 1 4 A1 A2 L b1 b e Figure 25. 8-Lead, Dual Inline Package (DIP) Dimensions Symbol A A1 A2 b b1 D E E1 e L eB 2.921 8.509 0 6.223 9.017 0.381 3.175 3.302 1.524 0.457 9.271 7.620 6.350 2.540 3.302 9.017 7 3.810 9.525 15 0.115 0.335 0 6.477 0.245 10.160 0.355 3.429 Millimeter Min. Typ. Max. 5.334 0.015 0.125 0.130 0.060 0.018 0.365 0.300 0.250 0.100 0.130 0.355 7 0.150 0.375 15 0.255 0.400 0.135 Min. Inch Typ. Max. 0.210 Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. (c) 2007 Fairchild Semiconductor Corporation FAN6300 * Rev. 1.0.1 A www.fairchildsemi.com 13 FAN6300 -- Highly Integrated Quasi-Resonant Current Mode PWM Controller (c) 2007 Fairchild Semiconductor Corporation FAN6300 * Rev. 1.0.1 www.fairchildsemi.com 14 |
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